Self-timed divider based on RSD number system

This paper proposes a divider structure that combines a novel self-timed ring structure and a carry-propagation-free division algorithm. The self-timed ring structure enables the divider to compute at a speed comparable to that of previously designed dividers with less silicon area. By exploiting the carry-propagation-free division algorithm, we can achieve even better performance. We designed a layout of 54-bit divider using 1.2 m CMOS technology and measured the area and speed. We obtained a speed of 135 ns per worst case division on 5.7 mm2 of silicon area.